1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to circuit technology for achievement in large-scaling of a memory cell array.
2. Description of the Prior Art
FIG. 17 is a circuit diagram showing an example of a mask ROM configuration of a contact method (contact mask programming method) in accordance with a conventional semiconductor memory device. The mask ROM of the contact method makes it correspond to xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d of stored data whether a drain of a memory cell transistor is connected to a bit line, or not connected thereto, respectively. In FIG. 17, the conventional semiconductor memory device comprises memory cell arrays 1 and 2, column decoders 3 and 4, transistors 5 and 6 for precharge, readout circuits 7 and 8, and an output selection circuit 9.
The memory cell array 1 is configured so that memory cells M1 (i, j) (i=1xe2x88x92m, j=1xe2x88x92n) which consist of N-channel MOS transistors may be arranged in a matrix configuration, i.e., forming rows and columns.
Gates of the N-channel MOS transistors which configure each memory cell M1 (i, j) are connected in common to word lines every n memory cells M1 (i, j) which have the same numeric value i and are arranged in a row direction. In addition, sources of these N-channel MOS transistors are connected in common to source lines GL1i (i=1xe2x88x92m) every n memory cells M1 (i, j) which have the same numeric value i and are arranged in the row direction. Furthermore, when stored data of the memory cell M1 (i, j) is xe2x80x9c0xe2x80x9d, the drain of this N-channel MOS transistor is made to connect to a bit line BL1j (j=1xe2x88x92n), and when the stored data of the memory cell M1 (i, j) is xe2x80x9c1xe2x80x9d, it is brought to a floating state. In the discussion hereinafter, a gate, a drain, and a source of the each N-channel MOS transistor which configures the memory cell M1 (i, j) will simply be referred to as the gate, the drain, and the source of the memory cell M1 (i, j).
In the conventional example, the gates of n memory cells M1 (i, j) which have the same numeric value i and are arranged in the row direction are connected to word line terminals WLi (i=1xe2x88x92m), respectively, into which row selection signals are inputted. Moreover, the source lines GL1i (i=1xe2x88x92m) are connected to a ground terminal having a ground potential.
The memory cell array 2 is configured so that memory cells M2 (i, j) (i=1xe2x88x92m, j=1xe2x88x92n) which consist of N-channel MOS transistors may be arranged in the matrix configuration, i.e., forming rows and columns.
Gates of the N-channel MOS transistors which configure each memory cell M2 (i, j) are connected in common to the word lines every n memory cells M2 (i, j) which have the same numeric value i and are arranged in the row direction. Moreover, sources of these N-channel MOS transistors are connected in common to source lines GL2i (i=1xe2x88x92m) every n memory cells M2 (i, j) which have the same numeric value i and are arranged in the row direction. Furthermore, when stored data in the memory cell M2 (i, j) is xe2x80x9c0xe2x80x9d, the drain of this N-channel MOS transistor is made to connect to bit line BL2j (j=1xe2x88x92n), and when the stored data in the memory cell M2 (i, j) is xe2x80x9c1xe2x80x9d, it is brought to the floating state. In the discussion hereinafter, a gate, a drain, and a source of the each N-channel MOS transistor which configures the memory cell M2 (i, j) will simply be referred to as the gate, the drain, and the source of the memory cell M2 (i, j).
In the conventional example, the gates of n memory cells M2 (i, j) which have the same numeric value i and are arranged in the row direction are connected to the word line terminals WLi (i=1xe2x88x92m), respectively, into which the row selection signals are inputted. Moreover, source lines GL2i (i=1xe2x88x92m) are connected to the ground terminal having the ground potential.
The column decoder 3 consists of P-channel MOS transistors Q1Pj (j=1xe2x88x92n) and N-channel MOS transistors Q1Nj (j=1xe2x88x92n). All sources of the P-channel MOS transistors Q1Pj (j=1xe2x88x92n) and drains of N-channel MOS transistors Q1Nj (j=1xe2x88x92n) are connected in common. Moreover, gates of the P-channel MOS transistors Q1Pj (j=1xe2x88x92n) are connected to column selection signal lines CLPj (j=1xe2x88x92n), respectively, and drains thereof are connected to bit lines BL1j (j=1xe2x88x92n), respectively. Moreover, gates of the N-channel MOS transistors Q1Nj (j=1xe2x88x92n) are connected to column selection signal lines CLNj (j=1xe2x88x92n), respectively, and sources thereof are connected to bit lines BL1j (j=1xe2x88x92n), respectively.
The column decoder 4 consists of P-channel MOS transistors Q2Pj (j=1xe2x88x92n) and N-channel MOS transistors Q2Nj (j=1xe2x88x92n). All sources of the P-channel MOS transistors Q2Pj (j=1xe2x88x92n) and drains of N-channel MOS transistors Q2Nj (j=1xe2x88x92n) are connected in common. Moreover, gates of the P-channel MOS transistors Q2Pj (j=1xe2x88x92n) are connected to the column selection signal lines CLPj (j=1xe2x88x92n), respectively, and drains thereof are connected to the bit lines BL2j (j=1xe2x88x92n), respectively. Moreover, gates of the N-channel MOS transistors Q2Nj (j=1xe2x88x92n) are connected to the column selection signal lines CLNj (j=1xe2x88x92n), respectively, and sources thereof are connected to the bit lines BL2j (j=1xe2x88x92n), respectively.
The transistor 5 for precharge consists of a P-channel MOS transistor. Then, a gate of the transistor 5 is connected to a precharge control signal line PCLK1, a source thereof is connected to a power supply terminal having a power supply potential, and a drain thereof is connected to the sources of the P-channel MOS transistors Q1Pj (j=1xe2x88x92n) and the drains of the N-channel MOS transistors Q1Nj (j=1xe2x88x92n) which configure the column decoder 3.
The transistor 6 for precharge consists of a P-channel MOS transistor. Then, a gate of the transistor 6 is connected to a precharge control signal line PCLK2, a source thereof is connected to the power supply terminal having the power supply potential, and a drain thereof is connected to the sources of the P-channel MOS transistors Q2Pj (j=1xe2x88x92n) and the drains of the N-channel MOS transistors Q2Nj (j=1xe2x88x92n) which configure the column decoder 4.
The readout circuit 7, whose input is connected to the drain of the transistor 5 for precharge, and the sources of the P-channel MOS transistors Q1Pj (j=1xe2x88x92n) and the drains of the N-channel MOS transistors Q1Nj (j=1xe2x88x92n) which configure the column decoder 3, and outputs data to a readout data line SOUT1. In the conventional example, assuming that when the stored data in the memory cell M1 (i, j) is xe2x80x9c0xe2x80x9d, the readout data line SOUT1 is brought to a low level, and when the stored data in the memory cell M1 (i, j) is xe2x80x9c1xe2x80x9d, the readout data line SOUT1 is brought to a high level.
The readout circuit 8, whose input is connected to the drain of the transistor 6 for precharge, and the sources of the P-channel MOS transistors Q2Pj (j=1xe2x88x92n) and the drains of the N-channel MOS transistors Q2Nj (j=1xe2x88x92n) which configure the column decoder 4, outputs data to a readout data line SOUT2. In the conventional example, assuming that when the stored data in the memory cell M2 (i, j) is xe2x80x9c0xe2x80x9d, the readout data line SOUT2 is brought to the low level, and when the stored data in the memory cell M2 (i, j) is xe2x80x9c1xe2x80x9d, the readout data line SOUT2 is brought to the high level.
The output selection circuit 9, into which signals of the readout data lines SOUT1 and SOUT2, and a readout data selection line SEL are inputted, outputs data to an output terminal DOUT. In the conventional example, assuming that while the readout data selection SEL stays in the low level, the output terminal DOUT outputs the data of the readout data line SOUT1, and while the readout data selection SEL stays in the high level, the output terminal DOUT outputs the data of the readout data line SOUT2.
Using the timing chart in FIG. 18, a description will be made of an operation for reading the data of the memory cell M1 (1, 1) in the semiconductor memory device configured as mentioned above. In signal waveforms of a bit line BL11, the readout data line SOUT1, and the output terminal DOUT shown in FIG. 18, solid lines show a case where the drain of the memory cell M1 (1, 1) is not connected to the bit line BL11, and dotted lines show a case where the drain of the memory cell M1 (1, 1) is connected to the bit line BL11.
First, among the column selection signal lines CLPj (j=1xe2x88x92n) and the column selection signal lines CLNj (j=1xe2x88x92n), a column selection signal line CLP1 is made a transition to the low level and column selection signal lines CLP2-CLPn are made the transition to the high level, and further, a column selection signal line CLN1 is made the transition to the high level and the column selection signal lines CLN2-CLNn are made the transition to the low level. Thereby, among the transistors Q1Pj (j=1xe2x88x92n) and the Q1Nj (j=1xe2x88x92n) which configure the column decoder 3, a transistor Q1P1 and a transistor Q1N1 are brought to an ON state, and other transistors Q1P2-Q1Pn and the transistors Q1N2-Q1Nn are brought to an OFF state. Moreover, all word line terminals WL1-WLm are made the transition to the low level.
Next, the precharge control signal line PCLK1 is brought to the low level only for a period t, and the transistor 5 for precharge is brought to the ON state for a constant period of time. Thereby, the bit line BL11 is charged to bring it to the high level.
After the bit line BL11 is brought to the high level, the word line terminal WL1 is made the transition from the low level being a non-selection state to the high level being a selection state. Thereby, when the drain of the memory cell M1 (1, 1) is connected to the bit line BL11, the electric charge charged in the bit line BL11 is discharged by the memory cell M1 (1, 1), and the bit line BL11 is brought to the low level. Moreover, when the drain of the memory cell M1 (1, 1) is not connected to the bit line BL11, the electric charge charged in the bit line BL11 is not discharged by the memory cell M1 (1, 1), and the bit line BL11 keeps the high level.
Consequently, in the readout circuit 7, when the drain of the memory cell M1 (1, 1) is connected to the bit line BL11, the readout data line SOUT1 is brought to the low level. Moreover, when the drain of the memory cell M1 (1, 1) is not connected to the bit line BL11, the readout data line SOUT1 is brought to the high level. At this time, by bringing the readout data selection SEL to the low level, the output selection circuit 9 outputs the data of the same level as the readout data line SOUT1 to the output terminal DOUT.
The conventional semiconductor memory devices have the following problems.
In the semiconductor memory device, since the drains of a plurality of the memory cells, whose source potential are set at the ground potential, are connected to one bit line, a steady state current due to an off-leak current of the memory cells is generated in the bit lines. Accordingly, the number of memory cells connected to the bit lines has been limited to the number the same as can be precharged up to a desired potential, even when the steady state current is generated by the off-leak current.
Particularly, in recent years, it is needed to increase the number of the memory cells connected to one bit line for the purpose of increasing the memory capacity according to advanced features of equipment. Especially, it should be recognized that the off-leak current of the transistor caused by fine patterning is acceleratively increasing, and the above-mentioned problems have been major concerns for achieving high performance of the semiconductor memory device.
The present invention overcomes the problems seen in the conventional semiconductor memory device described above, and by reducing the off-leak current of the memory cells connected to the bit line for reading, and thereby, enabling the increase in the number of the memory cells connected to the bit lines, that is, being capable of realizing an increase in the memory capacity is provided.
In order to achieve the object described above, the semiconductor memory device in accordance with the present invention employs a configuration where the source potential of the memory cells is set at a desired potential.
The semiconductor memory device according to a 1st invention comprises: a memory cell array having transistors for forming a plurality of memory cells arranged in a matrix configuration, and including a plurality of word lines, bit lines, and source lines connected to gates, drains, and sources of the transistors respectively; and a source potential control circuit for selectively setting potentials of the source lines according to the row selection signals for selecting word lines.
Then, the source potential control circuit sets potentials of source lines, out of the source lines, connected to unselected memory cells, in accordance with the row selection signals, at a potential different from a potential of a source line connected to memory cells being selected by the row selection signals so that the off-leak current of transistors included in memory cells being set as a non-selection state may decrease.
According to the semiconductor memory device of the 1st invention, it becomes possible to precharge the bit lines up to the desired potential even when a number of memory cells are connected by setting the source potential of the memory cell transistors at the arbitrary potential, without reducing the number of the memory cells connected to one bit line because of the off-leak current value of the transistors. Accordingly, a number of memory cells can be connected thereto and the large-scaling of the memory capacity of the semiconductor memory device can be achieved easily.
In the configuration of the semiconductor memory device according to the 1st invention, it is preferable to configure that the source potential control circuit sets a source potential of transistors for memory cells being selected by the row selection signals for selecting the word line at a ground potential, and sets a source potential of transistors for memory cells being set as a non-selection state by the row selection signals at the power supply potential.
According to the semiconductor memory device of the above-mentioned configuration, the same effect as that of the semiconductor memory device of the 1st invention is provided.
In the configuration of the semiconductor memory device having the source potential control circuit configured as described above, the source potential control circuit comprises, for example, inverters each for receiving a corresponding one of the row selection signals as an input, and providing an output to sources of corresponding ones of the transistors which receive the corresponding one of the row selection signals.
According to the semiconductor memory device of the above-mentioned configuration, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 2nd invention comprises: a memory cell array having transistors for forming a plurality of memory cells arranged in a matrix configuration, and including a plurality of word lines, bit lines, and source lines connected to gates, drains, and sources of the transistors respectively; and a source potential control circuit for setting a source potential of the transistors for memory cells being selected by row selection signals for selecting the word lines at a ground potential, and for setting a source potential of transistors for memory cells being set as a non-selection state by the row selection signals at a floating potential.
According to the semiconductor memory device of the 2nd invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
In the semiconductor memory device according to the 2nd invention, the source potential control circuit comprises, for example, transistors each receiving a corresponding one of the row selection signals to gate thereof, having a source connected to the ground terminal, and having a drain connected to sources of corresponding ones of the transistors which receive the corresponding one of the row selection signals.
According to the semiconductor memory device of the above-mentioned configuration, the same effect as that of the semiconductor memory device of the 1st invention is provided.
In the semiconductor memory device according to the 1st invention, it is preferable to configure the source potential control circuit that a source potential of transistors for memory cells selected by the row selection signals for selecting the word line is set at a ground potential, and a source potential of transistors for memory cells being set as a non-selection state by the row selection signals are set at an intermediate potential between the power supply potential and the ground potential.
According to the semiconductor memory device of the above-mentioned configuration, the same effect as that of the semiconductor memory device of the 1st invention is provided.
In the semiconductor memory device according to the configuration described as above, the source potential control circuit comprises: inverters which receives, for example, the row selection signals as inputs; 1st transistors each having a gate connected to an output of a corresponding one of the inverters, having a drain connected to a power supply terminal, and having a source connected to sources of corresponding ones of the transistors which receive a corresponding one of the row selection signals; and 2nd transistors each having a gate receiving a corresponding one of the row selection signals, having a sources connected to the ground potential, and having a drains connected to sources of corresponding ones of the transistors which receive the corresponding one of the row selection signals.
According to the semiconductor memory device of this configuration, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 4th invention comprises: in the configuration of the semiconductor memory device according to the 1st invention, the plurality of memory cells arranged into a plurality of memory cell arrays, and the semiconductor memory device further comprises: a 1st repeat circuit including 1st inverters connected to corresponding ones of the word lines at inputs thereof, and 2nd inverters connected to outputs of the 1st inverters at inputs thereof; and a 2nd repeat circuit including 3rd inverters connected to corresponding ones of the source lines at inputs thereof and 4th inverters connected to outputs of the 3rd inverters at inputs thereof.
Then, in the 1st repeat circuit, the outputs of the 2nd inverters are connected to word lines provided in a memory cell array different from a memory cell array in which word lines connected to the inputs of the 1st inverters are provided. Moreover, in the 2nd repeat circuit, the outputs of the 4th inverters are connected to source lines provided in a memory cell array different from a memory cell array in which source lines connected to the input of the 3rd inverters are provided. Furthermore, the 1st repeat circuit and the 2nd repeat circuit are formed between at least two of the memory cell arrays.
According to the semiconductor memory device of the 3rd invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 4th invention comprises: in the configuration of the semiconductor memory device according to the 1st invention, the plurality of memory cells arranged into a plurality of memory cell arrays, and the semiconductor memory device further comprises: a repeat circuit including 1st inverters connected to corresponding ones of source lines at inputs thereof and 2nd inverters connected to outputs of the 1st inverters at inputs thereof.
Then, in the repeat circuit, the outputs of the 2nd inverters are connected to source lines provided in a memory cell array different from a memory cell array in which source lines connected to the inputs of the 1st inverters are provided. Moreover, the repeat circuit is formed between at least two of the memory cell arrays.
According to the semiconductor memory device of the 4th invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 4th invention comprises: in the configuration of the semiconductor memory device according to the 1st invention, the plurality of memory cells arranged into a plurality of memory cell arrays, and the semiconductor memory device further comprises: 1st inverters connected to word lines at inputs thereof and to the source lines at outputs thereof; and 2nd inverters connected to the source lines at inputs thereof and to the word lines at outputs thereof.
Then, the outputs of the 1st inverters are connected to source lines provided in a memory cell array different from a memory cell array in which word lines connected to the inputs of the 1st inverters are provided. Moreover, the outputs of the 2nd inverters are connected to word lines provided in a memory cell array different from a memory cell array in which source lines connected to the inputs of the 2nd inverters are provided. Furthermore, the 1st inverters and the 2nd inverters are formed between at least two of the memory cell arrays.
According to the semiconductor memory device of the 5th invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 4th invention comprises: in the configuration of the semiconductor memory device according to the 1st invention, the plurality of memory cells arranged into a plurality of memory cell arrays, and the semiconductor memory device further comprises: a repeat circuit including inverters connected to corresponding ones of word lines at inputs thereof, and connected to corresponding ones of the source lines at outputs thereof.
In addition, the repeat circuit is formed between at least two of the memory cell arrays.
According to the semiconductor memory device of the 6th invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 4th invention comprises: in the configuration of the semiconductor memory device according to the 1st invention, the plurality of memory cells arranged into a plurality of memory cell arrays, and the semiconductor memory device further comprises: a repeat circuit including inverters connected to corresponding ones of the source lines at inputs thereof, and connected to corresponding ones of the word lines at outputs thereof. In addition, the repeat circuit is formed between at least two of the memory cell arrays.
According to the semiconductor memory device of the 7th invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 4th invention comprises: in the configuration of the semiconductor memory device according to the 1st invention, the plurality of memory cells arranged into a plurality of memory cell arrays, and the semiconductor memory device further comprises: a 1st repeat circuit including inverters connected to corresponding ones of the word lines at inputs thereof, and connected to corresponding ones of the source lines; and a 2nd repeat circuit including inverters connected to the source lines to inputs, and connecting word lines of the same rows as the inputs to the outputs.
In addition, the 1st repeat circuit and the 2nd repeat circuit are each formed between at least two of the memory cell arrays.
According to the semiconductor memory device of the 8th invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 9th invention comprises: a plurality of memory cell arrays having transistors for forming a plurality of memory cells in a matrix configuration, and including a plurality of wordlines, bit lines, and source lines connected to gates, drains, and sources of the transistors respectively; and a source potential control circuit for receiving the row selection signals for selecting the word lines and memory cell array selection signals provided for respective memory cell arrays at inputs thereof, respectively, for supplying outputs to respective source lines in a corresponding one of the memory cell arrays, and for setting the potential of source lines connected to transistors included in memory cells selected by the memory cell array selection signal and the row selection signals at the ground potential.
Then, the source potential control circuit is formed in each memory cell array.
According to the semiconductor memory device of the 9th invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
In the 9th configuration according to the invention, the source potential control circuit comprises NAND circuits for receiving, for example, the row selection signals for selecting the word line and the memory cell array selection signals provided for respective memory cell arrays at inputs thereof, respectively, and for providing the outputs to respective source lines in the corresponding one of the memory cell array.
According to the semiconductor memory device of the above-mentioned configuration, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 10th invention comprises: a memory cell array having transistors for forming a plurality of memory cells in a matrix configuration, and including a plurality of word lines, bit lines, and source lines connected to gates, drains, and sources of the transistors respectively; and a plurality of source line potential control circuits each connected to a source selection line at inputs thereof and connected to a plurality of source lines at outputs thereof.
Then, the plurality of source line potential control circuits set a potential of source lines connected to transistors included in memory cells selected by the row selection signals for selecting the word line at the ground potential.
According to the semiconductor memory device of the 10th invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.
The semiconductor memory device according to a 11th invention comprises a memory cell array having transistors for forming a plurality of memory cells in a matrix configuration, and including word lines, bit lines, and source lines connected to gates, drains, and sources of the transistors respectively, and a plurality of inverters for receiving source potential control signals at inputs thereof and providing outputs to a plurality of source lines.
Then, only an output potential of an inverter, out of said inverters, connected to a source line of transistors included in memory cells selected by the row selection signal is set at the ground potential.
According to the semiconductor memory device of the 11th invention, the same effect as that of the semiconductor memory device of the 1st invention is provided.